A standard test flow in the 93k environment follows a specific hierarchy outlined in the manual:
Efficiently managing large pattern files is a recurring theme in the manual. It provides instructions on converting third-party formats (like WGL or STIL) into the native 93k binary format. Key Calibration and Maintenance Procedures
The first line of defense to ensure the DUT is seated correctly. DC Parametrics: Measuring leakage currents ( IILcap I sub cap I cap L end-sub IIHcap I sub cap I cap H end-sub ) and power consumption ( IDDQcap I sub cap D cap D cap Q end-sub verigy 93k tester manual
This is a software-driven routine that adjusts for internal tester skews. It should be performed weekly or whenever the test head temperature shifts significantly.
Containing the pin electronics and cooling systems. A standard test flow in the 93k environment
Used for high-precision applications, this calibrates specific pins to the Device Under Test (DUT) interface board level, compensating for traces and socket parasitics.
To ensure repeatable results across different testers, the Verigy 93k manual emphasizes strict calibration routines. DC Parametrics: Measuring leakage currents ( IILcap I
When the tester behaves unexpectedly, the manual suggests a "divide and conquer" approach. First, verify the hardware by swapping a suspected bad PE card with a known good one. Second, use the tool in SmarTest to inspect real-time waveforms. This allows you to see exactly where a timing edge is falling relative to the data window.
💡 Always maintain a "Golden Device." If a test fails across multiple units, run the Golden Device to determine if the issue lies with the tester hardware or the test program itself.
Executing patterns at speed to verify logic gates.